Super-coherent multiprocessor system bus protocols
Superscalar microprocessor employing a data cache capable of per
Superscalar microprocessor employing a data cache capable of...
Superscalar microprocessor employing away prediction structure
Superscalar microprocessor including a cache configured to detec
Superscalar microprocessor including a decoded instruction cache
Superscalar microprocessor including a reorder buffer which dete
Superscalar processor employing a high performance write...
Superscaler processor and method for efficiently recovering...
Supplying voltage to a memory module
Support for exhaustion recovery in a data processing system...
Support for single-node quorum in a two-node nodeset for a...
Supporting directory-based cache coherence in an...
Supporting multiple outstanding requests to multiple targets...
Supporting speculative modification in a data cache
Supporting speculative modification in a data cache
Supporting un-buffered memory modules on a platform...
Surface computer and computing method using the same
Surface computer and computing method using the same
Surface level sparing in disk drives