Superscalar microprocessor employing a data cache capable of per

Details Superscalar microprocessor employing a data cache capable of per Superscalar microprocessor employing a data cache capable of per

1997-06-03

1999-11-16

Donaghue, Larry D.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

712218, 712 23, 711204, 711128, G06F 1576

Patent

active

059875615

ABSTRACT:
A superscalar microprocessor employing a data cache configured to perform store accesses in a single clock cycle is provided. The superscalar microprocessor speculatively stores data within a predicted way of the data cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete, utilizing a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The superscalar microprocessor may therefore be capable of high frequency operation.

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