Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-09-28
2010-12-28
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S101000
Reexamination Certificate
active
07861053
ABSTRACT:
A RDIMM enabled memory controller may support a UDIMM by way of a register chip and a PLL chip being implemented in operational relationship with a memory slot and a memory controller configured to support a RDIMM. The memory controller may drive address and control signals from the memory controller to the register chip, and the address and control signals may be provided from the register chip to the memory slot after one clock cycle, in response to the register chip latching onto the address and control signals from the memory controller on a rising clock edge.
REFERENCES:
patent: 7289383 (2007-10-01), Cornelius
patent: 2006/0039204 (2006-02-01), Cornelius
patent: 2006/0259666 (2006-11-01), Lee
patent: 2007/0008809 (2007-01-01), Kim
patent: 2008/0065786 (2008-03-01), Baska et al.
Intel Corporation, 66/100 MHz PC SDRAM 64-Bit Non-ECC/Parity 144 Pin Unbuffered SO-DIMM Specification, Revision 1.0, Feb. 1999.
Hewlett-Packard. “Memory technology evolution: an overview of system memory technologies,” technology brief, 7th edition. 2003.
Chuin Ooi Ping
Murugesu Sivakumar
Srivastava Durgesh
Wah Kok Lye
Bataille Pierre-Michel
Intel Corporation
Jordan IP Law, PC
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