Hardware emulation of parallel ATA drives with serial ATA...

Hardware enforced virtual sequentiality

Hardware hashing of an input of a content addressable memory...

Hardware implementation of an N-way dynamic linked list

Hardware initialization of a synchronous memory

Hardware mechanism for managing cache structures in a data...

Hardware mechanism for optimizing instruction and data prefetchi

Hardware prefetch system based on transfer request address...

Hardware support for partitioning a multiprocessor system to...

Hardware updated metadata for non-volatile mass storage cache

Hardware virtual machine instruction processor

Hardware-assisted tuple space

Hardware-based encryption/decryption employing dual ported...

Hardware-based translating virtualization switch

Hardware-managed programmable associativity caching mechanism mo

Hardware-managed programmable congruence class caching mechanism

Harvard architecture microprocessor having a linear...

Hash Cam having a reduced size memory array and its application

Hash CAM having a reduced width comparison circuitry and its...

Hash equation for MAC addresses that supports cache entry...