Hardware-managed programmable congruence class caching mechanism

Details Hardware-managed programmable congruence class caching mechanism Hardware-managed programmable congruence class caching mechanism

1997-04-14

1999-11-09

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, 711118, G06F 1208

Patent

active

059833220

ABSTRACT:
A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information. In this manner, a procedure running on the processor and allocating memory blocks to the cache such that the original addresses, if applied to the mapping function, would result in striding of the cache, runs more efficiently by using the encoded addresses to result in less striding of the cache.

REFERENCES:
patent: 3840863 (1974-10-01), Fuqua et al.
patent: 4315312 (1982-02-01), Schmidt
patent: 4797814 (1989-01-01), Brenza
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5058003 (1991-10-01), White
patent: 5133061 (1992-07-01), Melton et al.
patent: 5357623 (1994-10-01), Megory-Cohen
patent: 5410663 (1995-04-01), Blackburn et al.
patent: 5509135 (1996-04-01), Steely, Jr.
patent: 5640534 (1997-06-01), Liu et al.
patent: 5890221 (1999-03-01), Liu et al.
patent: 5893930 (1999-04-01), Song
Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Cache, Yau-Tsun Steven Li et al., IEEE Transactions on Computers, pp. 254-263, 1996.
Stack Evaluation of Arbitrary Set Associative Multiprocessor Caches, Yuguang Wu et al., IEEE Transactions on Parallel and Distributed Systems, vol. 6, No. 9, pp. 930-942, Sep. 1995.
Evaluating Associativity in CPU Caches, Mark D. Hill et al. IEEE Transactions on Computers, vol. 38, No. 12, pp. 1612-1630, Dec. 1989.
Sampling of Cache Congruence Classes, Lishing Liu et al., IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, No. 2, pp. 552-557, 1992.

Affiliated with

Also associated with

Rating

Hardware-managed programmable congruence class caching mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hardware-managed programmable congruence class caching mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware-managed programmable congruence class caching mechanism will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1470307