Hardware implementation of an N-way dynamic linked list

Details Hardware implementation of an N-way dynamic linked list Hardware implementation of an N-way dynamic linked list

2006-04-25

2006-04-25

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

Reexamination Certificate

active

07035988

ABSTRACT:
A hardware-implemented N-way dynamic link list is disclosed. The linked list memory structure comprises two basic parts for each stored location (entry)—a data element and pointer to the next element. Separate memory components provide a data organization that efficiently accesses any of N queues.

REFERENCES:
patent: 5838915 (1998-11-01), Klausmeier et al.
patent: 6430666 (2002-08-01), Roth
patent: 6694388 (2004-02-01), Schzukin et al.
patent: 2002/0029327 (2002-03-01), Roth
patent: 2003/0120879 (2003-06-01), Chen et al.
patent: 2004/0073553 (2004-04-01), Brown et al.
patent: 2004/0181504 (2004-09-01), Chang et al.
patent: 2004/0257891 (2004-12-01), Kim et al.
patent: 2005/0234933 (2005-10-01), Lin
patent: 2005/0235129 (2005-10-01), Sokol

Affiliated with

Also associated with

Rating

Hardware implementation of an N-way dynamic linked list does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hardware implementation of an N-way dynamic linked list, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware implementation of an N-way dynamic linked list will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3575563