Speed optimal bit ordering in a cache memory
Speed selective table scan operation
SPI bank addressing scheme for memory densities above 128Mb
Spillover slot
Spin-wheel SDRAM access scheduler for high performance...
Spinlock for shared memory
Spiral cache memory and method of operating a spiral cache
Splash tables: an efficient hash scheme for processors
Splash tables: an efficient hash scheme for processors
Split control for IP read and write cache misses
Split pending buffer with concurrent access of requests and...
Split sparse directory for a distributed shared memory...
Split write data processing mechanism for memory controllers uti
Split write data processing mechanism for memory controllers...
Split-SMP computer system configured to operate in a protected m
SRAM controller for parallel processor architecture and...
SRAM controller for parallel processor architecture...
SRAM with tag and data arrays for private external...
Sram with tag and data arrays for private external...
SRAM write partitioning