Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-01-16
2004-04-20
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C711S154000, C711S109000, C711S110000, C710S058000, C710S061000, C710S052000, C713S500000, C713S600000
Reexamination Certificate
active
06725347
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to microprocessor access to outside memory and in particular to a design of an on-chip memory controller in a computer system that optimizes memory access.
BACKGROUND OF THE INVENTION
In computer operations, a memory control unit (MCU) associated with a microprocessor performs input/output transactions with an outside memory device. The microprocessor may operate alone, or may operate in a multi-processor environment. The target outside memory device, in current systems, is typically a Synchronous Dynamic Random Access Memory (SDRAM). With rapid advances in integrated circuits involving semiconductor technologies, it is now possible to integrate the MCU inside the microprocessor chip. This integration of the MCU allows the MCU to operate at the speed of the processor clock, which is many times faster than the clock speed at which the SDRAM operates.
The memory in the SDRAM is organized in banks. Typically, the number of memory banks may range from 4 to 16 or more. Corresponding to each of these SDRAM banks, there is a memory request queue in the MCU. A memory request basically involves a Row Address Strobe (RAS) command and a Column Address Strobe (CAS) command for accessing data in a memory bank. The MCU has a request scheduler and a RAS/CAS generator which will process requests for all the memory banks in an orderly and timely manner. For correct and efficient SDRAM access, ensuring correct timing of issuing these RAS/CAS commands is critical.
In a SDRAM, after a single memory access, each bank has to perform a precharge operation for memory refresh before a new RAS command can be sent. This means that there is no new memory request to this bank during the precharge operation. However, while one bank is busy doing the precharge, the request scheduler could initiate a RAS command for another bank. A SDRAM will have many memory banks and, correspondingly, a MCU will be handling as many request queues. The request scheduler of the MCU must resolve all timing conflicts among different banks and sort through the legal combinations in time so that the RAS and CAS commands are formed and issued at the right time for each and every bank.
Implementation of a memory request scheduler for a MCU becomes increasingly complex as the number of memory banks increases. For example, arbitrating among 4 banks requires sorting through 4096 possibilities to get a legal and optimum setting. Therefore, a software implementation will be very slow and inefficient. There exists a need for a method that can be implemented in the hardware so as to achieve optimum SDRAM access performance at a very low hardware cost.
SUMMARY OF THE INVENTION
In some aspects the invention relates to an apparatus for controlling a memory device comprising: a command spin wheel that schedules a read or a write command for the memory device; a read spin wheel that ensures correct timing of the read command; and a write spin wheel that ensures correct timing of the write command.
In an alternative embodiment, the invention relates to an on-chip memory control unit for an SDRAM that serves a plurality of microprocessors, comprising: a command spin wheel that schedules read and write commands on a SDRAM command bus in a first-in, first-out order, the command spin wheel comprising, an auto-incremental release pointer, an auto-incremental CAS pointer, and an auto-incremental schedule pointer; a read spin wheel that ensures a proper timing sequence of a read command in a first-in, first-out order, the read spin wheel comprising, a data read request pointer, and a schedule pointer; and a write spin wheel that ensures a proper timing sequence of a write command in a first-in, first-out order, the write spin wheel comprising, a data push request pointer, and a schedule pointer.
In an alternative embodiment, the invention relates to an apparatus for controlling a memory device comprising: means for scheduling a read command or a write command for the memory device; means for ensuring a proper timing sequence for the read command; and means for ensuring a proper timing sequence for the write command.
In an alternative embodiment, the invention relates to a method for controlling a memory device comprising: scheduling a read or a write command for the memory device; ensuring a proper timing sequence for a read command; and ensuring a proper timing sequence for a write command.
The advantages of the invention include, at least, a multiple memory bank request sorting problem has been decomposed into a much simpler problem of data structures handled with logic circuits. The complicated timing design and access-scheduling problem has a slow, software-based solution. With this invention, it is now possible to implement a very fast, hardware-based solution, which can be realized in an on-chip MCU. By time efficient use of memory control and data buses, computer memory access performance of a MCU can now be optimized.
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International Search Report dated Apr. 23, 2003 ( 1 page).
Tong Duong
Yang Liuxi
Kim Hong
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
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