Speed optimal bit ordering in a cache memory

Details Speed optimal bit ordering in a cache memory Speed optimal bit ordering in a cache memory

1996-08-29

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 5, G06F 1300

Patent

active

058025650

ABSTRACT:
Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache. In this manner, a single control line can latch all of the elements in a logical register.

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patent: 5493506 (1996-02-01), Sakashita et al.
patent: 5517440 (1996-05-01), Widigen et al.

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