Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-07-30
2004-04-27
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S158000, C710S039000
Reexamination Certificate
active
06728845
ABSTRACT:
BACKGROUND
This invention relates to memory controllers particularly for use in parallel processing systems.
Parallel processing is an efficient form of information processing of concurrent events in a computing process. Parallel processing demands concurrent execution of many programs in a computer, in contrast to sequential processing. In the context of a parallel processor, parallelism involves doing more than one thing at the same time. Unlike a serial paradigm where all tasks are performed sequentially at a single station or a pipelined machine where tasks are performed at specialized stations, with parallel processing, a plurality of stations are provided with each capable of performing all tasks. That is, in general all or a plurality of the stations work simultaneously and independently on the same or common elements of a problem. Certain problems are suitable for solution by applying parallel processing.
Memory systems used in parallel processing tasks can be inefficient. Memory systems can have a dead time i.e., bubble that can either be 1 or 2 cycles depending on the type of memory device employed.
SUMMARY
According to an aspect of the present invention, a controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue and a first read/write queue that holds memory references from a core processor. The controller also includes control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference instruction from one of the queues.
One or more of the following advantages may be provided by one or more aspects of the invention.
The memory controller performs memory reference sorting to minimize delays (bubbles) in a pipeline from an interface to memory. The memory system is designed to be flooded with memory requests that are independent in nature. The memory controller enables memory reference sorting which reduces dead time or a bubble that occurs with accesses to static random access memory (SRAM). With memory references to SRAM, switching current direction on signal lines between reads and writes produces a bubble or a dead time while waiting for current to settle on conductors coupling the SRAM to the SRAM controller. That is, the drivers that drive current on the bus need to settle out prior to changing states. Thus, repetitive cycles of a read followed by a write can degrade peak bandwidth. Memory reference sorting organizes references to memory such that long strings of reads can be followed by long strings of writes. This can be used to minimize dead time in the pipeline to effectively achieve closer to maximum available bandwidth. Grouping reads and writes improves cycle-time by eliminating dead cycles. The memory controller performs memory reference sorting based on a read memory reference.
The memory controller can also include a lock lookup device for look-ups of read locks. The address and command queue also includes a read lock fail queue, to hold read memory reference requests that fail because of a lock existing on a portion of memory as determined by the lock lookup device.
REFERENCES:
patent: 3373408 (1968-03-01), Ling
patent: 5432918 (1995-07-01), Stamm
patent: 5630130 (1997-05-01), Perotto et al.
patent: 5649157 (1997-07-01), Williams
patent: 5659687 (1997-08-01), Kim et al.
patent: 5721870 (1998-02-01), Matsumoto
patent: 5905876 (1999-05-01), Pawlowski et al.
patent: 5948081 (1999-09-01), Foster
patent: 6070231 (2000-05-01), Ottinger
patent: 6092158 (2000-07-01), Harriman et al.
patent: 6182177 (2001-01-01), Harriman
patent: 6212611 (2001-04-01), Nizar et al.
patent: 6247025 (2001-06-01), Bacon
patent: 6256713 (2001-07-01), Audityan et al.
patent: 6427196 (2002-07-01), Adiletta et al.
“Multithreaded Processor Architectures”, G.T. Byrd et al., IEEE Spectrum, IEEE Inc., New York, US, vol. 32, No. 8, 8-1-95, pps. 38-46.
Adiletta Matthew J.
Cutter Daniel
Redfield James
Wheeler William
Wolrich Gilbert
Fish & Richardson P.C.
Gossage Glenn
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