SRAM write partitioning

Details SRAM write partitioning SRAM write partitioning

1996-11-25

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711104, G06F 1202

Patent

active

058601180

ABSTRACT:
A circuit and method for generating a global write enable signal for use in an SRAM partitioning scheme. The global write enable signal is generated by taking a combination of the individual write enable signals and presenting them as a global write control. The global write control signal allows all of the particular data groups to have common timing. The particular SRAM data groups may implement configuration dependent functionality which can be grouped with other data partitions in the array. A particular SRAM data group may share local decode and write control circuitry with other data groups. Particular SRAM data groups not selected for writing have their write data inputs driven to an inactive state during the WRITE.

REFERENCES:
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5535164 (1996-07-01), Adams et al.
"A Circuit Design Of Intelligent Cache Dram With Automatic Write-Back Capability"IEEE Journal of Solid-State Circuits. vol. 26, No. 4, Apr. 1991 pp. 560-565.

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