SPI bank addressing scheme for memory densities above 128Mb

Details SPI bank addressing scheme for memory densities above 128Mb SPI bank addressing scheme for memory densities above 128Mb

2011-07-12

2011-07-12

Patel, Hetul (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S165000, C711SE12008, C710S022000, C710S023000

Reexamination Certificate

active

07979625

ABSTRACT:
Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.

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Notice of Allowance dated Apr. 15, 2011 for U.S. Appl. No. 11/945,316.19 Pages.

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