Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-02
1999-07-13
Dinh, Dung C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39520046, 711152, 711153, C06F 15163
Patent
active
059238470
ABSTRACT:
A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction. The top repeater transmits the global transaction to all repeaters in the system. Subsequently, the transaction is retransmitted upon all of the local buses. In one embodiment, a transaction is determined to be local or global based upon the address partition containing the address. The address space of the computer system is divided into multiple address partitions. Each partition is defined to be either local or global, and additional properties are defined for each partition.
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Hagersten Erik E.
Hill Mark D.
Dinh Dung C.
Kivlin B. Noel
Sun Microsystems Inc.
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