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Recovery mechanism for L1 data cache parity errors

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Recovery of data using write request copies in delta queue

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Recycle mechanism for a processing agent

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Recycling partially-stale flash blocks using a sliding...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Redirecting external memory allocation operations to an...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Redistribution of memory to reduce computer system power...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Reduced instruction processor/storage controller interface

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reduced latency memory configuration method using...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reduced memory traffic via detection and tracking of...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reduced pin system interface

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reduced synchronization reservation system and method for a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Reducing bandwidth and areas needed for non-inclusive memory hie

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing bus width by data compaction

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Reducing cache misses by snarfing writebacks in non-inclusive me

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing cache pollution of a software controlled cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing communication for reads and updates in distributed...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing content addressable memory (CAM) power consumption...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reducing content addressable memory (CAM) power consumption...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reducing data copy operations for writing data from a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing delay of command completion due to overlap condition

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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