Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-02-21
2002-05-28
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S170000
Reexamination Certificate
active
06397299
ABSTRACT:
1. FIELD OF THE INVENTION
The present invention relates generally to memory subsystems in electronic devices. More particularly, the present invention relates to reducing latency in memory subsystems.
2. BACKGROUND OF THE INVENTION
Computer systems typically comprise at least one processor, a memory subsystem, at least one system controller and one or more peripherals (such as PCI devices) operably connected by various buses, including a host bus operably connected between the processor and the system controller. The processor may include an internal level one (L
1
) cache. The memory subsystem typically comprises system or main memory external to both the processor and the system controller and a level two (L
2
) cache internal to the system controller. Together, the L
1
cache and the memory subsystem (L
2
cache and main memory) comprise a memory hierarchy.
The system controller includes logic for, in conjunction with the processor and peripheral devices, controlling the transfer of data and information between the processor and peripheral devices and the memory subsystem. For example, if a processor issues a read transaction, the processor will determine whether the requested data is stored in the L
1
cache. If the read request is a “miss” in the L
1
cache, during a subsequent clock cycle, the system controller will determine whether the requested data is stored in the L
2
cache. If the read request is a miss in the L
2
cache, during yet another subsequent clock cycle, the system controller will attempt to access the requested data in the main memory. At this point, given the relatively larger size of main memory, the slower speed of main memory, and the distance of main memory from the CPU, a number of clock cycles may be required decode the address of the read request and access the requested data in the main memory.
Thus, when accessing main memory (after L
1
and L
2
cache misses), the computer system experiences a relative degree of latency. This latency may be increased in multi-processor/multi-controller systems, wherein each processor and each system controller may have a respective L
1
and L
2
cache. In order to preserve coherency between the respective L
1
and L
2
caches and the main memory, respective L
1
and L
2
cache controllers must monitor buses within the computer system (typically the host bus) to determine if another processor or peripheral device has modified data in an L
1
cache, L
2
cache or main memory. If modifications have been made, the caches and main memory must be updated accordingly. Monitoring the memory hierarchy in this manner may be referred to as snooping. A snoop operation requires at least one clock cycle to perform, thus adding to the relative degree of latency within these types of computer systems.
To deal with the latency (i.e., to prevent transactions that may “interfere” with the memory access request until the memory access request has been completed), the computer system may interrupt, stall or insert a number of wait states into various operations and transactions. This results in a relatively slower computer system with relatively slower processing and reduced computer system throughput. Operating such a computer system is relatively time consuming and costly.
Thus, there exists a need in the art for apparatus and methods for reducing the inherent latency in accessing memory subsystem.
In still other computer systems, a system controller may have an internal or “embedded” peripheral. In these computer systems, the embedded peripheral is an integral component of the system controller. The embedded peripheral may be a “secondary” processor (i.e., a processor without the power, capabilities and intelligence of the main or external processor) and may be utilized to relieve the computational burden on the main processor. Because these embedded peripherals lack the sophistication of the main processor (or, for that matter, most external peripherals), in current computer systems, the embedded peripheral cannot access the memory subsystem. As such, in current computer systems, the embedded peripheral must be provided with a dedicated memory exclusively utilized by the embedded peripheral. In current computer systems, this embedded peripheral dedicated memory is external to the system controller or “off chip”. Providing this dedicated memory “off chip” adds latency to embedded peripheral's memory accesses and consumes valuable space within the computer system. Additionally, the exclusivity of the dedicated memory decreases the versatility of the computer system.
Thus, there exists a need in the art for apparatus and methods for reducing latency in embedded peripheral dedicated memory accesses and for increasing the versatility of embedded peripheral dedicated memory.
3. SUMMARY OF THE INVENTION
The present invention relates to a method in a computer system, for configuring a memory subsystem, comprising selecting a subset of main memory, integrating the subset of main memory within the computer system such that the subset is physically distinct from the main memory and configuring the subset of main memory as noncacheable memory.
REFERENCES:
patent: 4797850 (1989-01-01), Amitai
patent: 4903239 (1990-02-01), Akashi
patent: 5161218 (1992-11-01), Catlin
patent: 5249160 (1993-09-01), Wu et al.
patent: 5317709 (1994-05-01), Sugimoto
patent: 5325504 (1994-06-01), Tipley et al.
patent: 5388073 (1995-02-01), Usami et al.
patent: 5434969 (1995-07-01), Heilveil et al.
patent: 5477488 (1995-12-01), Subramani
patent: 5546352 (1996-08-01), Sato et al.
patent: 5583822 (1996-12-01), Rao
patent: 5586286 (1996-12-01), Santeler et al.
patent: 5602771 (1997-02-01), Kajigaya et al.
patent: 5638532 (1997-06-01), Frame et al.
patent: 5659715 (1997-08-01), Wu et al.
patent: 5818464 (1998-10-01), Wade
patent: 5909696 (1999-06-01), Reinhardt et al.
patent: 6003120 (1999-12-01), Hardin
patent: 6178481 (2001-01-01), Krueger et al.
Dosey & Whitney LLP
Portka Gary J.
Yoo Do Hyun
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