Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-09-30
2000-06-06
Robertson, David L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711146, G06F 1200
Patent
active
060732121
ABSTRACT:
An apparatus and method for optimizing a non-inclusive hierarchical cache memory system that includes a first and second cache for storing information. The first and second cache are arranged in an hierarchical manner such as a level two and level three cache in a cache system having three levels of cache. The level two and level three cache hold information non-inclusively, while a dual directory holds tags and states that are duplicates of the tags and states held for the level two cache. All snoop requests (snoops) are passed to the dual directory by a snoop queue. The dual directory is used to determine whether a snoop request sent by snoop queue is relevant to the contents of level two cache, avoiding the need to send the snoop request to level two cache if there is a "miss" in the dual directory. This increases the available cache bandwidth that can be made available by second cache since the number of snoops appropriating the cache bandwidth of second cache are reduced by the filtering effect of dual directory. Also, the third cache is limited to holding read-only information and receiving write-invalidation snoop requests. Only snoops relating to write-invalidation requests are passed to a directory holding tags and state information corresponding to the third cache. Limiting snoop requests to write invalidation requests minimizes snoop requests to third cache, increasing the amount of cache memory bandwidth available for servicing catch fetches from third cache. In the event that a cache hit occurs in third cache, the information found in third cache must be transferred to second cache before a modification can be made to that information.
REFERENCES:
patent: 5155828 (1992-10-01), LaFetra et al.
patent: 5155832 (1992-10-01), Hunt
patent: 5303362 (1994-04-01), Butts, Jr. et al.
patent: 5369753 (1994-11-01), Tipley
patent: 5386547 (1995-01-01), Jouppi
patent: 5398325 (1995-03-01), Chang et al.
patent: 5432918 (1995-07-01), Stamm
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5564035 (1996-10-01), Lai
patent: 5577227 (1996-11-01), Finnell et al.
patent: 5581725 (1996-12-01), Nakayama
patent: 5603004 (1997-02-01), Kurpanek et al.
patent: 5651135 (1997-07-01), Hatakeyama
patent: 5671231 (1997-09-01), Cooper
patent: 5696936 (1997-12-01), Church et al.
patent: 5717890 (1998-02-01), Ichida et al.
patent: 5943686 (1999-08-01), Arimilli et al.
Handy, Jim; The Cache Memory Book; Academic Press, Inc., 1993; pp. 132-133.
Afek, et al., "A Lazy Cache Algorithm," Association for Computing Machinery, 0-89791-323-X, 1989, pp. 209-223.
Brown, G., "Asynchronous multicaches," Distributed Computing, vol. 4, pp. 31-36; 1990.
IBM Technical Disclosure Bullentin, Jan. 1998, vol. 30, No. 8, p. 33.
Hayes Norman M.
Hetherington Ricky C.
Kuttanna Belliappa M.
Pong Fong
Thatipelli Krishna M.
Robertson David L.
Sun Microsystems Inc.
LandOfFree
Reducing bandwidth and areas needed for non-inclusive memory hie does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reducing bandwidth and areas needed for non-inclusive memory hie, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing bandwidth and areas needed for non-inclusive memory hie will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2223883