Reduced instruction processor/storage controller interface

Details Reduced instruction processor/storage controller interface Reduced instruction processor/storage controller interface

1997-01-21

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711124, 711128, 711167, 711169, 395280, 365227, G06F 1200

Patent

active

058600930

ABSTRACT:
Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.

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