Reducing cache pollution of a software controlled cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S137000, C711SE12002, C712S207000

Reexamination Certificate

active

08055849

ABSTRACT:
Reducing cache pollution of a software controlled cache is provided. A request is received to prefetch data into the software controlled cache. A first designator is set for a first cache access to a first value. If there is the second cache access to prefetch, a determination is made as to whether data associated with the second cache access exists in the software controlled cache. If the data is in the software controlled cache, a determination is made as to whether a second value of a second designator is greater than the first value of the first cache access. If the second value fails to be greater than the first value, the position of the first cache access and the second cache access in a cache line is swapped. The first value is decremented by a predetermined amount and the second value is replaced to equal the first value.

REFERENCES:
patent: 5796971 (1998-08-01), Emberson
patent: 5809566 (1998-09-01), Charney et al.
patent: 5838945 (1998-11-01), Emberson
patent: 5940838 (1999-08-01), Schmuck et al.
patent: 6578130 (2003-06-01), Barrick et al.
patent: 6721943 (2004-04-01), Krishnaiyer et al.
patent: 6728837 (2004-04-01), Wilkes et al.
patent: 6772415 (2004-08-01), Danckaert et al.
patent: 7155575 (2006-12-01), Krishnaiyer et al.
patent: 7243195 (2007-07-01), O'Brien et al.
patent: 2003/0105926 (2003-06-01), Rodriguez
patent: 2005/0102294 (2005-05-01), Coldewey
patent: 2006/0090036 (2006-04-01), Zohar et al.
patent: 2007/0005901 (2007-01-01), Kellar
patent: 2007/0130428 (2007-06-01), Ohba
patent: 2008/0005473 (2008-01-01), Chen et al.
patent: 2009/0049256 (2009-02-01), Hughes et al.
patent: 2009/0254733 (2009-10-01), Chen et al.
patent: 2009/0254895 (2009-10-01), Chen et al.
Vellanki et al., “A Cost-Benefit Scheme for High Performance Predictive Prefetching”, SC'99, ACM, 1999, pp. 1-18.
Ramachandran et al., “Architectureal mechanisms for explicit communication in shared memory multiprocessors”, Proceedings of the 1995 ACM/IEEE Supercomputing Conference, Dec. 3-8, 1995, vol. 2, pp. 1737-1775.
Lu et al., “The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System”, Proceedings of the 36th International Symposium on Microarchitecture (MICRO-36'03), IEEE, 2003, 11 pages.
Bernstein et al., “Context-based prefetch—an optimization for implementing objects on relations”, The VLDB Journal (2000) 9: 177-189.
Knight et al., “Compilation for Explicitly Managed Memory Hierarchies”, PPoPP'07, ACM, Mar. 14-17, 2007, pp. 226-236.
Cantin et al., “Stealth Prefetching”, ASPLOS'06, ACM, Oct. 21-25, 2006, pp. 274-282.
Chen et al., “Prefetching Irregular References for Software Cache on Cell”, ACM, CGO'08, Boston Massachusetts, Apr. 5-10, 2008, 10 pages.
Chen et al., “Optimizing the Use of Static Buffers for DMA on a Cell Chip”, LCPC 2006, LNCS 4382, 2007, pp. 314-329.
Min et al., “Combined Compile-time and Runtime-driven, Pro-active Data Movement in Software DSM Systems”, School of Electrical and Computer Engineering, Seventh Workshop on Languages, Compilers, and Run-time Support for Scalable Sytems (LCR'04), Purdue University, Oct. 2004, pp. 1-6.
Youfeng Wu, “Efficient Discovery of Regular Stride Patterns in Irregular Programs and Its Use in Compiler Prefetching”, PLDI'02, ACM, Jun. 17-19, 2002, pp. 210-221.
Yang et al., “Space/Time-Efficient Scheduling and Executin of Parallel Irregular Computations”, ACM Transactions on Programming Languages and Systems, vol. 20, No. 6, Nov. 1998, pp. 1195-1222.
Zhang et al., “Accelerating and Adapting Precomputation Threads for Efficient Prefetching”, 13th International Symposium on High Performance Computer Architecture, IEEE, 2007, pp. 85-95.
Bernstein et al., “Context-based prefetch—an optimization for implementing objects on relations”, The VLDB Journal, Springer-Verlag, 2000, 9: 177-189.
Ramachandran et al., “Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors”, Proceedings of the 1995 ACM/IEEE Supercomputing Conference, vol. 2, Dec. 3-8, 1995, pp. 1737-1775.
Vellanki et al., “A Cost-Benefit Scheme for High Performance Predictive Prefetching”, SC '99, ACM, 1999, pp. 1-18.
Zucker et al., “An Automated Method for Software Controlled Cache Prefetching”, Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, vol. 7, 1998, 9 pages.
U.S. Appl. No. 12/062,559.
U.S. Appl. No. 12/062,579.

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