Reduced memory traffic via detection and tracking of...

Details Reduced memory traffic via detection and tracking of... Reduced memory traffic via detection and tracking of...

2006-08-24

2009-08-04

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000

Reexamination Certificate

active

07571286

ABSTRACT:
A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.

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Tang, “Selective Invalidation Scheme for Software MP Cache Coherence Control”, IBM Technical Disclosure Bulletin, No. 3, pp. 244-246, Aug. 1992.
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Lepak et al., “Temporally Silent Stores”, ACM Digital Library, Oct. 2002, pp. 1-12.

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