Reducing bus width by data compaction

Details Reducing bus width by data compaction Reducing bus width by data compaction

2007-07-10

2007-07-10

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S172000, C711S130000

Reexamination Certificate

active

10721316

ABSTRACT:
An integrated circuit device includes a processing component and a cache, which is arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having an address length of ml bits. First and second buses are coupled between the processing component and the cache, the buses having bus widths of n1and n2bits, respectively, such that n1<m1. The processing component and the cache each include a respective address bus expander coupled to the first bus in order to compact at least some of the memory addresses for transmission over the first bus so that each of the at least some memory addresses is transmitted over the first bus in one cycle of the first bus.

REFERENCES:
Citron, Daniel et al., “Creating a Wider Bus Using Caching Techniques”, Proceedings of the First IEEE Symposium on High-Performance Computer Architecture, Jan. 1995, pp. 90-99.
Yang, Jun et al., “Frequent Value Compression in Data Caches”, Proceedings of the 33rd International Symposium on Microarchitecture, Dec. 2000, pp. 258-275.

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