Enhanced dynamic address translation with load real address...
Enhanced microprocessor or microcontroller
Enhanced microprocessor or microcontroller
Enhanced shadow page table algorithms
Entry lockdown within a translation lookaside buffer mechanism
Error detection in cache tag array using valid vector
Ethernet controller
Even/odd cache directory mechanism
Event address register history buffers for supporting...
Exclusive access for logical blocks
Extended page mode with a skipped logical addressing for an embe
Extended page mode with memory address translation using a linea
Extended translation lookaside buffer with fine-grain state...
Extracted-index addressing of byte-addressable memories