Error detection in cache tag array using valid vector

Details Error detection in cache tag array using valid vector Error detection in cache tag array using valid vector

2000-12-28

2003-01-21

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S100000, C711S118000, C711S200000, C714S048000

Reexamination Certificate

active

06510506

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to computer architecture. In particular, the invention relates to cache memory.
2. Description of Related Art
Soft errors are errors caused by temporary disruption of memory cells. In high performance processors, it is desirable to reduce the soft error rate (SER) and/or the failure in time (FIT) as much as possible. Undetected soft errors in processor cache lead to corrupt data and may result in unacceptable performance. When soft errors occur in a cache internal to a processor, such as an instruction cache, the erroneous instruction code may cause damaging effects to subsequent processing units in the processing chain.
An internal cache unit usually consists of a translation look-aside buffer (TLB) unit for virtual to physical address translation and an associated tag array unit. In a typical cache access, an index portion of the virtual address is used to index the TLB unit while a tag portion is used to look up the tag array unit. The contents of the looked up tag entry from the tag array unit are compared with the indexed TLB entry to determine if the access results in a miss or a hit. If there is a soft error in the tag array, the comparison may generate incorrect result, leading to subsequent errors.
Existing techniques to reduce the SER or FIT in cache typically include use of extra hardware or redundancy such as duplicating the tag structure. These techniques have a number of drawbacks. First, the amount of overhead for the extra hardware may become large. Second, the additional circuits may consume a large amount of power. Third, the interconnections may be complex, having additional lines connecting to the word line of the memory.


REFERENCES:
patent: 5410668 (1995-04-01), Hilton
patent: 5793941 (1998-08-01), Pencis et al.
patent: 6216200 (2001-04-01), Yeager
patent: 6237079 (2001-05-01), Stoney
patent: 6349379 (2002-02-01), Gibson et al.

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