Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Patent
1998-01-15
2000-02-01
Robertson, David L.
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
711202, G06F 1200
Patent
active
060214821
ABSTRACT:
The present disclosure concerns a method and apparatus for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device. The memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data. Each paragraph is comprised of a plurality of contiguous columns. A physical address identifies a location of a paragraph in the memory device. To map the logical addresses to physical addresses, a determination must be made as to whether the row and column portions of each logical address identify a physical address location including parity data. If a logical address identifies a physical address location in the memory device including parity data, then the logical address is incremented until the row and column portions of the logical address identify a physical address location not including parity data. The mapping is then conducted by setting the column and row portions of the physical address to the column and row portions of one of the: (i) logical address upon determining that the logical address does not identify a physical address location including parity data and (ii) the incremented logical address upon determining that the logical address identifies a physical address location including parity data.
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Peng Steven K.
Wu Frank Yuhhaw
Robertson David L.
Seagate Technology Inc.
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