Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2008-01-11
2011-10-18
Rojas, Midys (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S206000, C711S209000
Reexamination Certificate
active
08041922
ABSTRACT:
What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.
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Greiner Dan F.
Heller Lisa C.
Osisek Damian L.
Pfeffer Erwin
Sittmann Gustav E.
Campbell John E.
International Business Machines - Corporation
Rojas Midys
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