Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-09-06
2005-09-06
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S159000
Reexamination Certificate
active
06941442
ABSTRACT:
A translation lookaside buffer mechanism is described incorporating a set associative translation lookaside buffer operating in parallel with a fully associative translation lookaside buffer. Lockdown entries are stored within the fully associative translation lookaside buffer and non-lockdown entries are stored within the set associative translation lookaside buffer. Victim selection for the fully associative translation lookaside buffer18is performed using a control register within a coprocessor which is set under operating system software control.
REFERENCES:
patent: 6138225 (2000-10-01), Upton et al.
patent: 6223263 (2001-04-01), Mathews et al.
patent: 6374341 (2002-04-01), Nijhawan et al.
patent: 6553477 (2003-04-01), Krishna et al.
patent: 6625715 (2003-09-01), Mathews
Anderson Matthew D.
ARM Limited
Nixon & Vanderhye P.C.
Thomas Shane
LandOfFree
Entry lockdown within a translation lookaside buffer mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Entry lockdown within a translation lookaside buffer mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Entry lockdown within a translation lookaside buffer mechanism will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3445496