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Flexible control and/or status register configuration

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flexible data transfer to and from external device of...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flexible microcontroller architecture

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flexible routing and addressing

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flexible switch-based I/O system interconnect

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flexible width data protocol

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flow architecture for remote high-speed interface application

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flow-splitting and buffering PCI express switch to reduce...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Flushing stale data from a PCI bus system read prefetch buffer

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Fly-by support module for a peripheral bus

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Form factor converter and tester in an open architecture...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Framework and method for inter-element channel transmission

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
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Fully connected cache coherent multiprocessing systems

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