Fly-by support module for a peripheral bus

Details Fly-by support module for a peripheral bus Fly-by support module for a peripheral bus

2000-08-22

2003-12-09

Vo, Tim (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S022000, C710S028000

Reexamination Certificate

active

06662258

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a module that provides fly-by support for a peripheral bus, which enables communication between master modules and slave modules. More specifically, the present invention relates to a module that enables a master module to control the direct transfer of data between a slave module and a fly-by slave module.
DISCUSSION OF RELATED ART
FIG. 1
is a block diagram of a prior art system
100
that includes a bus master
101
, a first bus slave
102
, a second bus slave
103
and a peripheral bus
104
. Traditionally, bus master
101
transfers data from first bus slave
102
to second bus slave
103
as follows. First, bus master
101
reads the data from first bus slave
102
. Bus master
101
then stores the data read from first bus slave
102
. Subsequently, bus master
101
transfers the data to second bus slave
103
. While this approach only requires the coordination of two devices (i.e., a master and a slave) at any given time, the time required to complete the entire data transfer is relatively long because all data must be routed through bus master
101
. It would therefore be desirable to have a method for directly transferring data between two bus slaves under the control of a bus master.
SUMMARY
Accordingly, the present invention provides a high performance, fully synchronous system having a master device, a slave device and a fly-by slave device, each of which is coupled to a peripheral bus. The master device is configured to control the transfer of data directly between the slave device and the fly-by slave device without buffering the data.
To transfer data from the slave device to the fly-by slave device, the bus master initiates a read operation in the slave device, such that the slave device provides data on the peripheral bus under the control of the bus master. At the same time, the master device initiates a write operation in the fly-by slave device using a dedicated connection between the master device and the fly-by slave device. The fly-by slave device then snoops the data provided on the peripheral bus by the slave device. The fly-by slave device then performs a write operation using the data snooped from the peripheral bus. Advantageously, the master device does not have to buffer the data read from the slave device.
To transfer data from the fly-by slave device to the slave device, the master device initiates a read operation in the fly-by slave device using a dedicated connection between the master device and the fly-by slave device, such that the fly-by slave device provides data on the peripheral bus. At the same time, the master device initiates a write operation in the slave device, such that the data provided on the peripheral bus by the fly-by slave device is written directly to the slave device under the control of the master device. Again, the master device does not have to buffer the data read from the fly-by slave device.
In one embodiment, the transfer of data on the peripheral bus is fully synchronous, with burst transfers being supported. Other signals can be used to control the transfer of data between the slave device and the fly-by slave device on the peripheral bus. For example, the fly-by slave device can provide a control signal to the master device to indicate when it is ready to perform a read operation or a write operation. In addition, the master device can provide a control signal to identify the last transaction of a read or write operation.
In one embodiment, the master device is a DMA controller and the slave device is a memory controller. The fly-by slave device can be, for example, an Ethernet system, a universal serial bus (USB) system, a TDM peripheral, or an asynchronous transfer mode (ATM) system.


REFERENCES:
patent: 5007012 (1991-04-01), Dujari
patent: 5416916 (1995-05-01), Bayle
patent: 5781749 (1998-07-01), Le Quere
patent: 5828856 (1998-10-01), Bowes et al.
patent: 6055584 (2000-04-01), Bridges et al.

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