Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-03-13
2008-10-21
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
07441064
ABSTRACT:
A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is transferred for each of four beats during each of four consecutive cycles of the bus clock. The data signal group may include multiple data strobes, such as first and second data strobes for latching first and third doublewords and third and fourth data strobes for latching second and fourth doublewords during each cycle of the bus clock. Each doubleword may be provided on first and second data portions of the data signal group. The first and second data strobes may latch data on the first data portion and the third and fourth data strobes may latch data on the second data portion.
REFERENCES:
patent: 4796232 (1989-01-01), House
patent: 5255378 (1993-10-01), Crawford et al.
patent: 5537624 (1996-07-01), Whitesell
patent: 5561780 (1996-10-01), Glew et al.
patent: 5640517 (1997-06-01), Parks et al.
patent: 5644788 (1997-07-01), Courtright et al.
patent: 5835741 (1998-11-01), Elkhoury et al.
patent: 5901298 (1999-05-01), Cummins et al.
patent: 5915126 (1999-06-01), Maule et al.
patent: 5919254 (1999-07-01), Pawlowski et al.
patent: 5944806 (1999-08-01), Melvin et al.
patent: 5960453 (1999-09-01), Pawlowski
patent: 6012116 (2000-01-01), Aybay et al.
patent: 6032225 (2000-02-01), Shiell et al.
patent: 6311245 (2001-10-01), Klein
patent: 6356270 (2002-03-01), Pentkovski et al.
patent: 6405280 (2002-06-01), Ryan
patent: 6405285 (2002-06-01), Arimilli et al.
patent: 6434654 (2002-08-01), Story et al.
patent: 6505259 (2003-01-01), Garcia et al.
patent: 6523109 (2003-02-01), Meier
patent: 6587862 (2003-07-01), Henderson
patent: 6601121 (2003-07-01), Singh et al.
patent: 6609171 (2003-08-01), Singh et al.
patent: 6671752 (2003-12-01), Rao et al.
patent: 6742160 (2004-05-01), Greiner
patent: 6804735 (2004-10-01), Singh et al.
patent: 6807592 (2004-10-01), Singh et al.
patent: 6907487 (2005-06-01), Singh et al.
patent: 6954208 (2005-10-01), Doyle et al.
patent: 7130952 (2006-10-01), Nanki et al.
patent: 7206865 (2007-04-01), Creta et al.
patent: 2002/0029307 (2002-03-01), Singh et al.
patent: 2002/0103948 (2002-08-01), Owen et al.
patent: 2003/0088799 (2003-05-01), Bodas
patent: 2004/0199723 (2004-10-01), Shelor
patent: 2005/0066114 (2005-03-01), Barth et al.
patent: 2006/0053243 (2006-03-01), David et al.
patent: 2006/0190677 (2006-08-01), Janzen
patent: 1242898 (2002-09-01), None
patent: 1416390 (2004-05-01), None
Auve Glenn A.
Huffman James W.
Huffman Richard K.
Stanford Gary R.
Via Technologies Inc.
LandOfFree
Flexible width data protocol does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flexible width data protocol, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flexible width data protocol will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3989862