Flow-splitting and buffering PCI express switch to reduce...

Details Flow-splitting and buffering PCI express switch to reduce... Flow-splitting and buffering PCI express switch to reduce...

2007-12-11

2007-12-11

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S316000

Reexamination Certificate

active

11308597

ABSTRACT:
An enhanced Peripheral Component Interconnect Express (PCIe) switch eliminates or reduces head-of-line blocking for memory reads initiated by peripheral endpoint devices. A memory-read request packet from a first peripheral endpoint device is intercepted by the enhanced PCIe switch, which generates a series of substitute request packets to the root complex and memory. The same requestor ID is used in all packets, but the original tag is replaced with a sequence of substitute tags in the substitute packets. The switch receives a sequence of reply packets with memory-read data, replaces substitute tags with original tags, and sends the reply packets to the peripheral endpoint device. Substitute request packets for different peripheral endpoint devices are alternately sent from the switch to the root complex to prevent head-of-line blocking by one peripheral endpoint device. The amount of data in each substitute request packet is smaller than the original requests to reduce blocking latencies.

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