First-in-first-out (FIFO) memory for buffering packet...
Flexible and error resistant data buffering and connectivity
Flexible and error resistant data buffering and connectivity
Flexible and error resistant data buffering and connectivity
Flexible FIFO system for interfacing between datapaths of...
Flow control for digital signal processing to support data...
Flow control for media streaming
Flow control mechanism
Frame transfer method and device
Free packet buffer allocation
Gear box for multiple clock domains
Generalized queue and specialized register configuration for...
Glitch suppression circuit and method
Grouping class sensitive queues
Hardware command block delivery queue for host adapters and othe
Hierarchical ring buffers for buffering data between processor a
High performance, variable data width FIFO buffer
High speed processor
High-speed internal bus architecture for an integrated circuit
Host bus adapter based scalable performance storage...