Generalized queue and specialized register configuration for...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering

Reexamination Certificate

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C710S036000, C710S039000, C710S057000, C711S147000, C711S154000

Reexamination Certificate

active

07093037

ABSTRACT:
Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notifications of queue and other conditions, selectivity in receiving and generating conditions, and the ability to combine data transfer and particular condition notifications in the same attention register.

REFERENCES:
patent: 5832262 (1998-11-01), Johnson et al.
patent: 6260057 (2001-07-01), Eykholt et al.
patent: 6725457 (2004-04-01), Priem et al.
patent: 6829660 (2004-12-01), Liu et al.
patent: 2003/0110325 (2003-06-01), Roach et al.
patent: 2003/0126320 (2003-07-01), Liu et al.

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