High-speed internal bus architecture for an integrated circuit

Details High-speed internal bus architecture for an integrated circuit High-speed internal bus architecture for an integrated circuit

2008-05-06

2008-05-06

Knoll, Clifford (Department: 2111)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S310000

Reexamination Certificate

active

07370127

ABSTRACT:
An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

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