Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-12-19
2011-11-22
Portka, Gary (Department: 2187)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S055000, C711S159000
Reexamination Certificate
active
08065450
ABSTRACT:
In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.
REFERENCES:
patent: 5535366 (1996-07-01), Pfeiffer et al.
patent: 6535516 (2003-03-01), Leu et al.
patent: 2007/0104187 (2007-05-01), Tatapudi et al.
patent: 11-102325 (1999-04-01), None
patent: 11-261569 (1999-09-01), None
patent: 2000-200210 (2000-07-01), None
Notification of Reason for Refusal dated Apr. 19, 2011, from corresponding Japanese Application No. 2006-349819.
Fujitsu Limited
Katten Muchin & Rosenman LLP
Portka Gary
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