High performance, variable data width FIFO buffer

Details High performance, variable data width FIFO buffer High performance, variable data width FIFO buffer

2000-08-31

2004-01-20

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S004000, C710S020000, C710S033000, C710S036000, C710S056000, C710S310000

Reexamination Certificate

active

06681273

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to data transfers in computer systems and, more particularly, to methods and apparatus for performing efficient, alignment-independent data transfers using an intelligent FIFO buffer.
BACKGROUND OF THE INVENTION
Computer systems frequently encounter the need to transfer blocks of data to or from memory. For example, direct memory access (DMA) is widely used to relieve the central processing unit (CPU) of the burden of moving blocks of data to or from memory. A DMA controller separate from the CPU allows the CPU or an external data source to specify a data transfer operation and to return to normal processing, while the DMA controller carries out the data transfer operation independently of the CPU. A DMA operation may be specified by a source starting address, a destination starting address and the number of data words to be transferred.
One application of DMA transfers is in digital signal processors, which are special purpose computers that are designed to optimize performance for digital signal processor applications. Digital signal processor applications are characterized by real-time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Some digital signal processor architectures have dual execution units and thus require large quantities of data for efficient operation. Data buses having widths of 64 bits allow the transfer of two 32-bit data words in a single clock cycle.
For maximum flexibility, both aligned and non-aligned memory accesses may be utilized. Aligned memory accesses are aligned to double 32-bit word boundaries, whereas non-aligned accesses are not aligned to double 32-bit word boundaries. Thus, a DMA transfer may have a source address that is aligned or non-aligned, and a destination address that is aligned or non-aligned. Depending on the source and destination addresses and the number of data words being transferred, several individual DMA transfers may be required to transfer a specified block of data.
Accordingly, there is a need for methods and apparatus for high speed data transfer of different numbers of data words, where the source and destination addresses may be aligned or non-aligned.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, apparatus is provided for transferring data words from a source to a destination. The apparatus comprises a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.
The datapath buffer may comprise a first-in, first-out (FIFO) datapath buffer. The first source transfer condition may comprise an aligned source address, and the second source transfer condition may comprise a non-aligned source address. The first destination transfer condition may comprise an aligned destination address, and the second destination transfer condition may comprise a non-aligned destination address. The first number of data words may comprise a double data word, and the second number of data words may comprise a single data word.
The datapath buffer may comprise a first set of storage locations, such as even FIFO locations, and a second set of storage locations, such as odd FIFO locations. The datapath buffer may further comprise write alignment logic for directing data words from high and low sections of the first data bus to the first and second sets of storage locations in response to a write align signal. The datapath buffer may further comprise read alignment logic for directing data words from the first and second sets of storage locations to high and low sections of the second data bus in response to a read align signal.
Preferably, the first number of data words is written in the datapath buffer or read from the datapath buffer in a single transfer cycle and the second number of data words is written in the datapath buffer or read from the datapath buffer in a single transfer cycle. The datapath buffer, the write control logic and the read control logic may be configured for bi-directional data transfer between the source and the destination.
According to another aspect of the invention, a method is provided for transferring data words from a source to a destination. The method comprises the steps of providing a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, writing a first number of data words in the datapath buffer in response to a first source transfer condition, writing a second number of data words in the datapath buffer in response to a second source transfer condition, reading the first number of data words from the datapath buffer in response to a first destination transfer condition, and reading the second number of data words from the datapath buffer in response to a second destination transfer condition.
The method may further comprise the steps of writing a third number of data words in the datapath buffer in response to a third source transfer condition, and reading the third number of data words from the datapath buffer in response to a third destination transfer condition.
According to a further aspect of the invention, apparatus for transferring data words comprises a datapath buffer coupled by a data bus to a source and write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition.
According to yet another aspect of the invention, apparatus for transferring data words comprises a datapath buffer coupled by a data bus to a destination and read control logic for reading a first number of data words from the datapath buffer in response to a first destination transfer condition and for reading a second number of data words from the datapath buffer in response to a second destination transfer condition.


REFERENCES:
patent: 5325486 (1994-06-01), Omori et al.
patent: 5740394 (1998-04-01), Minemura et al.
patent: 5996031 (1999-11-01), Lim et al.

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