Selectively deposited silicon oxide layers on a silicon...
Self adjusting transfer gate APS
Self aligned channel implantation
Self aligned double gate transistor having a strained...
Self aligned LOD antiblooming structure for solid-state imagers
Self aligned metal gates on high-k dielectrics
Self aligned method for differential oxidation rate at shallow t
Self aligned method of forming a semiconductor memory array...
Self aligned method of forming a semiconductor memory array...
Self masking contact using an angled implant
Self protected stacked NMOS with non-silicided region to protect
Self protecting bipolar SCR
Self protecting NLDMOS, DMOS and extended voltage NMOS devices
Self-aligned and process-adjusted high density power transistor
Self-aligned array contact for memory cells
Self-aligned bipolar transistor having recessed spacers and...
Self-aligned body contact for a semiconductor-on-insulator...
Self-aligned body tie for a partially depleted SOI device...
Self-aligned buried channel/junction stacked gate flash memory c
Self-Aligned buried contact pair