Self aligned double gate transistor having a strained...

Details Self aligned double gate transistor having a strained... Self aligned double gate transistor having a strained...

2005-02-15

2005-02-15

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S059000, C438S259000, C438S270000, C438S271000, C438S589000

Reexamination Certificate

active

06855982

ABSTRACT:
A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.

REFERENCES:
Huang et al., Sub 50 nm Fin FET: PMOS, 1999 (4 pages).

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