Self protected stacked NMOS with non-silicided region to protect

Details Self protected stacked NMOS with non-silicided region to protect Self protected stacked NMOS with non-silicided region to protect

1999-07-09

2000-10-31

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257360, 257546, H01L 2362

Patent

active

061406821

ABSTRACT:
A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included. Sets of cascode connected transistors in the plurality include a first diffusion region, a second diffusion region on a first side of and separated from the first diffusion region by a channel of a first transistor, a third diffusion region on a second side of and separated from the first diffusion region by a channel of the second transistor, a fourth diffusion region on a first side of and separated from the second diffusion region by a channel of a third transistor, a fifth diffusion region on a second side of and separated from the third diffusion region by a channel of a fourth transistor. Gate structures are formed over the channels of the first, second, third and fourth transistors. An interconnect structure couples the first diffusion region to the contact pad, the fourth and fifth diffusion regions to the second supply terminal, the gate structures of the first and second transistors to a first supply terminal, the gate structure of the third transistor to a selected one of the second supply terminal and a signal source, and the gate structure of the fourth transistor to a selected one of the signal source and the second supply terminal. The structure acts typically as a pull-down stage for an output driver on an integrated circuit. A pull-up transistor is included in the complete circuit. The diffusion regions between the first and third transistor and between the second and fourth transistor are formed without silicide.

REFERENCES:
patent: 5495118 (1996-02-01), Kinoshita et al.
patent: 5545909 (1996-08-01), Williams et al.
patent: 5631793 (1997-05-01), Ker et al.
patent: 5672896 (1997-09-01), Lee et al.
patent: 5679971 (1997-10-01), Tamba et al.
patent: 5780897 (1998-07-01), Krakauer
patent: 5847429 (1998-12-01), Lien et al.
Anderson, Warren R. and Krakauer, David B., "ESD Protection for Mixed Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration," EOS/ESD Symposium, 1998. pp. 54-62.
Hulett, Terrry V., "On Chip Protection of High Density NMOS Devices," Motorola Semiconductor Group, Austin, Texas, pp. 90-96.
Amerasekera, Ajith and Duvvury, Charvaka, ESD in Silicon Integrated Circuits, John Wiley & Sons, 1995, pp. 55-145.
Duvvury, C. et al., "A Summary of Most Effective Electrostatic Discharge Protection circuits for MOS Memories and their Observed Failure Modes," Texas Instruments Inc., Houston, Texas, pp. 181-184.

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