Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-11-01
2005-11-01
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000
Reexamination Certificate
active
06960810
ABSTRACT:
A silicon-on-insulator (SOI) device structure100formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.
REFERENCES:
patent: 5405795 (1995-04-01), Beyer et al.
patent: 5489792 (1996-02-01), Hu et al.
patent: 5920093 (1999-07-01), Huang et al.
patent: 6124613 (2000-09-01), Kokubun
patent: 6144072 (2000-11-01), Iwamatsu et al.
patent: 6307237 (2001-10-01), Erstad
patent: 6348714 (2002-02-01), Lin et al.
patent: 6353245 (2002-03-01), Unnikrishnan
patent: 6498371 (2002-12-01), Krishnan et al.
patent: 9-246562 (1997-09-01), None
patent: 09246562 (1997-09-01), None
Chuang, et al., SOI for Digital CMOS VLSI: Design Considerations and Advances Proceedings of the IEEE, vol. 86, No. 4, Apr. 1998.
Fechner, et al., “Radiation Hardened SOI CMOS and 1M SRAM”, 1997 IEEE International SOI Conference, Sep. 30-Oct. 2, 1997, p. 172.
Fechner, et al., “SHARP Isolation Technology for Radiation Hardened Submicron CMOS SOI”, Journal of Radiation Effects, Research and Engineering, vol. 13, No. 1, Jan. 1996, p. 106.
Kang, et al., “A Novel Body-tied Silicon-On-Insulator (SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode” ETRI Journal, vol. 17, No. 4, Jan. 1996.
Min, et al., “Partial Trench Isolated Body-tied (PTIBT) Structure for SOI Applications” IEEE International SOI Conference, Oct. 2001.
Pelloie, et al. “WP 25.2 SOI Technology Performance and Modeling” IEEE International Solid-State Circuits Conference, 1999.
“A RF Power LDMOS Device on SOI,” 1999 IEEE International SOI Conference, Oct. 1999.
International Search Report for PCT/US03/16556 Mailed Oct. 13, 2003.
Fourson George
Maldonado Julio
McDonnell Boehnen & Hulbert & Berghoff LLP
LandOfFree
Self-aligned body tie for a partially depleted SOI device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-aligned body tie for a partially depleted SOI device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned body tie for a partially depleted SOI device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3473615