Self-aligned array contact for memory cells

Details Self-aligned array contact for memory cells Self-aligned array contact for memory cells

2005-03-22

2005-03-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S301000, C257S305000, C257S306000, C257S307000

Reexamination Certificate

active

06870211

ABSTRACT:
A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

REFERENCES:
patent: 6262450 (2001-07-01), Kotecki et al.
patent: 6570208 (2003-05-01), Mandelman et al.
patent: 6600183 (2003-07-01), Visokay et al.
patent: 6737316 (2004-05-01), Lee
patent: 20020196651 (2002-12-01), Weis

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