SRAM cell employing tunnel switched diode

SRAM cell for soft-error rate reduction and cell stability...

SRAM cell having asymmetric pass gates

SRAM cell having increased cell ratio

SRAM cell having load thin film transistors

Sram cell structure

SRAM cell structure and circuits

SRAM cell using a CMOS compatible high gain gated lateral BJT

SRAM cell using tunnel current loading devices

SRAM cell using two single transistor inverters

SRAM cell using word line controlled pull-up NMOS transistors

SRAM cell utilizing bistable diode having GeSi structure therein

SRAM cell with column select line

SRAM cell with horizontal merged devices

SRAM cell with independent static noise margin, trip...

SRAM cell with intrinsically high stability and low leakage

SRAM cell with p-channel pull-up sources connected to bit lines

SRAM cell with read-disturb immunity

SRAM cell with separate read and write ports

SRAM cell without dedicated access transistors