SRAM cell with separate read and write ports

Details SRAM cell with separate read and write ports SRAM cell with separate read and write ports

2006-12-07

2010-02-09

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

07660149

ABSTRACT:
This invention discloses a dual port static random access memory (SRAM) cell, which comprises at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and an output terminals, at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively, a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line, and a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line.

REFERENCES:
patent: 6519204 (2003-02-01), Slamowitz et al.
patent: 6556487 (2003-04-01), Ratnakumar et al.
patent: 6958948 (2005-10-01), Shiraishi
patent: 7136296 (2006-11-01), Luk et al.
patent: 7376002 (2008-05-01), Nii
patent: 2003/0002328 (2003-01-01), Yamauchi
patent: 2003/0107913 (2003-06-01), Nii
patent: 2007/0279966 (2007-12-01), Houston

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