SRAM cell without dedicated access transistors

Details SRAM cell without dedicated access transistors SRAM cell without dedicated access transistors

2009-06-30

2011-12-06

Nguyen, Viet (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S174000, C365S188000

Reexamination Certificate

active

08072797

ABSTRACT:
A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

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