SRAM cell with independent static noise margin, trip...

Details SRAM cell with independent static noise margin, trip... SRAM cell with independent static noise margin, trip...

2008-06-10

2008-06-10

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S189050

Reexamination Certificate

active

07385840

ABSTRACT:
An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline. The cell also includes a first read driver connected between the first pass node and a source potential, and a control terminal of the first read driver connected to the second latch node of the second inverter.

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U.S. Appl. No. 11/202,141, filed Aug. 11, 2005, Houston.

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