SRAM cell for soft-error rate reduction and cell stability...

Details SRAM cell for soft-error rate reduction and cell stability... SRAM cell for soft-error rate reduction and cell stability...

2007-08-14

2007-08-14

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000, C365S104000

Reexamination Certificate

active

10926769

ABSTRACT:
An SRAM device includes a memory cell. The memory cell includes a first cross-coupled inverter and a second cross-coupled inverter, which is electrically connected to the first cross-coupled inverter. Each inverter includes a pull down device and a pull up device. The pull up device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pull down device is preferably within a range of about 1.5 to about 0.8. A channel area ratio of the pull up device to the pull down device is preferably within a range of about 3 to about 1. A pass gate device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pass gate device is preferably within a range of about 3.0 to about 1.2.

REFERENCES:
patent: 4750155 (1988-06-01), Hsieh
patent: 4821233 (1989-04-01), Hsieh
patent: 6341083 (2002-01-01), Wong
patent: 6510076 (2003-01-01), Lapadat et al.
patent: 2005/0023633 (2005-02-01), Yeo et al.

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