Mechanism for automatically enabling and disabling clock signals
Mechanism for coupling a wideband current signal between two...
Mechanism for generating precision user-programmable...
Mechanism for maintaining relatively constant gain in a...
Mechanism for minimizing current mirror transistor base...
Mechanism for minimizing undesirable effects of parasitic...
Mechanism for providing over-voltage protection during power...
Median peak detector for controlling disk pickup head
Median reference voltage selection circuit
Memory clock generation with configurable phase advance and...
Memory clock slowdown
Memory clock slowdown synthesis circuit
Memory device having a duty ratio corrector
Memory device having a duty ratio corrector
Memory device having an adjustable voltage swing setting
Memory device initialization
Memory device pump circuit with two booster circuits
Memory interface phase-shift circuitry to support multiple...
Memory reset apparatus
Memory system including a memory device having a controlled...