Memory clock slowdown

Details Memory clock slowdown Memory clock slowdown

2007-03-06

2007-03-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S160000

Reexamination Certificate

active

10741149

ABSTRACT:
Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

REFERENCES:
patent: 5142366 (1992-08-01), Brown et al.
patent: 5541646 (1996-07-01), Huang
patent: 6104222 (2000-08-01), Embree
patent: 6114987 (2000-09-01), Bjornholt
patent: 6127896 (2000-10-01), Burzio
patent: 6414555 (2002-07-01), Staszewski et al.
patent: 6463013 (2002-10-01), Liu et al.

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