Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-02-04
2002-04-23
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S147000
Reexamination Certificate
active
06377091
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronic circuits and more particularly to a mechanism for maintaining relatively constant gain in a multiple component apparatus.
BACKGROUND OF THE INVENTION
A phase-locked loop (PLL) is a mechanism that uses feedback to maintain a specific phase relationship between a reference signal and the output signal of the PLL. The ability of the PLL to maintain this specific phase relationship makes it useful in many different electronic circuit applications, including frequency synthesizers, analog and digital modulators and demodulators, and clock recovery circuits.
A typical PLL is shown in
FIG. 1
, wherein the PLL
110
comprises a phase frequency detector (PFD)
112
, a charge pump
114
, a loop filter
116
, a voltage controlled oscillator (VCO)
118
, and a feedback divider
120
. The output of the PLL is taken from the output of the VCO
118
, and this output is fed to the feedback divider
120
. In response, the feedback divider
120
generates a divided version of the PLL output, and provides the divided version as the feedback signal. The feedback signal and the reference signal are fed as inputs to the PFD
112
.
The function of the PFD
112
is to detect the difference in phase and frequency between the two input signals, and to generate output control signals UP and DOWN indicative of the phase and frequency differences. These control signals UP, DOWN are then fed as inputs to the charge pump
114
. In response, the charge pump
114
generates a net current in accordance with the input control signals UP, DOWN, to either charge or discharge the loop filter
116
to a particular voltage. It is the voltage on loop filter
116
that controls the frequency of the PLL output generated by the VCO
118
. Because of the feedback signal, the voltage present at the input of the VCO
118
is such that it causes the VCO
118
to generate a new PLL feedback signal having a frequency and phase closer to that of the reference signal. In this manner, the PLL
110
“pushes” the phase and frequency of the PLL feedback signal towards that of the reference signal. This feedback/adjustment process continues until the PLL feedback signal “locks on” to the phase and frequency of the reference signal.
The transfer function for the PLL
110
of
FIG. 1
is given as follows:
H
(
s
)
=
KcpKvco
(
1
+
τ
1
s
)
M
(
C1
+
C2
)
(
1
+
τ
2
s
)
s
2
where Kcp is the combined gain of the PFD
112
and the charge pump
114
;
Kvco is the gain of the VCO
118
;
M is the divisor of the feedback divider
120
;
C
1
and C
2
are the values of the capacitors C
1
and C
2
in the loop filter
116
;
&tgr;1=R
1
C
1
where R
1
is the value of the resistor R
1
in the loop filter
116
; and
&tgr;2=&tgr;1C
2
/(C
1
+C
2
).
From this equation, it is clear that the transfer function has one zero (a value of s where the numerator is zero), and three poles (a value of s where the denominator is zero). The zero occurs when s is −1/&tgr;1, and the poles occur when s is 0 (this pole occurs twice since s is squared) and when s is −1/&tgr;2. The transfer function defines the open loop gain of the PLL
110
in the complex s domain.
A plot of the open loop gain of the PLL
110
in the frequency domain is shown in FIG.
2
. In
FIG. 2
, there are three frequencies of note: (1) f
1
is the frequency at which the transfer function experiences its zero; (2) f
2
is the frequency at which the transfer function experiences its non-zero pole; and (3) fc is the crossover frequency at which the open loop gain of the PLL
110
is unity or 1 (i.e.
0
dB). Frequency f
1
is equal to 1/(2&pgr;&tgr;1) and frequency f
2
is equal to 1/(2&pgr;&tgr;2). Since f
1
and f
2
are a function of &tgr;1 and &tgr;2, and since &tgr;1 and &tgr;2 are in turn a function of R
1
, C
1
, and C
2
, f
1
and f
2
can be set with relative precision by assigning proper values to R
1
, C
1
, and C
2
. From a performance and implementation standpoint, it is desirable to set f
1
as high as possible and f
2
as low as possible. With a higher f
1
, smaller on-chip loop filter components can be used, and better phase noise performance is achieved due to higher loop gain. With a lower f
2
, greater attenuation of reference feed-through is achieved. Thus, to optimize results, the gap between f
1
and f
2
should be as small as possible.
Several factors limit how close f
1
and f
2
can be to each other, one of which is stability of the PLL
110
. To maintain stability, the unity gain crossover of the PLL
110
needs to occur between f
1
and f
2
(i.e. fc needs to be between f
1
and f
2
). If the gap between f
1
and f
2
is small, it requires that the crossover frequency fc be kept within a relatively small frequency band. This can be difficult to do, especially if the gains of the various components in the PLL
110
vary. More specifically, the crossover frequency fc is determined by the overall gain of the PLL
110
, which in turn is determined by the gains of the individual components, such as the charge pump
114
and the VCO
118
. If the gains of the individual components vary widely, thereby causing the overall gain of the PLL
110
to vary widely, then the crossover frequency will also vary widely. Unfortunately, due to factors such as operating conditions and processing variations, gain variations among the individual components is inevitable. Consequently, the crossover frequency fc currently cannot be determined or set with good precision. As a result, designers have been forced to widen the gap between f
1
and f
2
to ensure stability. As noted previously, widening the gap between f
1
and f
2
leads to less than optimal performance.
SUMMARY OF THE INVENTION
To overcome the shortcomings of the prior art, the present invention provides a mechanism for stabilizing the overall gain of a multi-component apparatus, such as a PLL. By maintaining the overall gain of the apparatus at a relatively constant level, the present invention makes it possible to set certain parameters, such as the unity crossover frequency of a PLL, with greater precision. By increasing the precision with which certain parameters may be set, the present invention makes it possible to derive better performance from the apparatus.
In accordance with one embodiment there is provided a gain adjustment circuit for maintaining the overall gain of a multi-component apparatus at a relatively constant level. In one embodiment, the multi-component apparatus in which the gain adjustment circuit may be implemented comprises a first component and a second component. The first component (e.g. a VCO) has a variable gain, and receives as input a control signal which determines the gain of the component. The second component (e.g. a charge pump) has an adjustable gain, and provides as output an output signal which affects the control signal fed to the first component. The gain adjustment circuit adjusts the adjustable gain of the second component based upon the control signal fed to the first component to maintain the overall gain of the components relatively constant. In carrying out this function, the gain adjustment circuit receives the control signal as input and provides an adjustment signal as output.
More specifically, based upon the control signal fed to the first component, the gain adjustment circuit determines whether the control signal is at a level which causes the variable gain of the first component to be high, or is at a level which causes the variable gain to be low. If the control signal is at a level which causes the variable gain to be high, then the gain adjustment circuit sets the adjustable gain of the second component to a low level. In one embodiment, this is done by providing a proper adjustment signal to the second component. On the other hand, if the control signal is at a level which causes the variable gain to be low, then the gain adjustment circuit sets the adjustable gain of the second component to a high l
Caviglia Tony L.
Matsuzaki John
Williams Stephen T.
Cadence Design Systems Inc.
Hickman Palermo Truong & Becker
Tra Quan
Truong Bobby K.
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