Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-06-25
2004-08-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C365S189090
Reexamination Certificate
active
06781439
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a pump circuit and, more specifically, to a semiconductor device including a booster circuit for boosting a power supply voltage up to a predetermined one or a negative voltage generating circuit for stepping it down to a predetermined one.
A nonvolatile semiconductor memory device of an EEPROM requires a voltage which is higher than a power supply voltage when data is written to or erased from a memory cell. Such a semiconductor device includes a booster circuit for boosting up a power supply voltage to generate a high voltage. In a case where the device requires a negative voltage, a power supply voltage is stepped down to generate a given negative voltage.
FIG. 22
illustrates an arrangement of a prior art booster circuit disclosed in J. F. Dickson, IEEE Journal of Solid State Circuits, Vol. SC-11, pp. 374-8, Jun. 1976, and
FIG. 23
shows an operating waveform of the circuit of FIG.
22
. In this booster circuit, N-channel MOS transistors (referred to as NMOS transistors hereinafter)
17
b
,
17
c
and
17
d
are diode-connected in series between a terminal
17
a
to which a power supply voltage Vcc is applied and an output node OUT. An oscillator
17
e
is constituted of a NAND circuit and a plurality of inverter circuits, and an inverter circuit
17
f
and a capacitor
17
g
are connected in series between an output terminal of the oscillator
17
e
and a connection node N
1
of the NMOS transistors
17
b
and
17
c
. Furthermore, inverter circuits
17
h
and
17
i
and a capacitor
17
j
are connected in series between the output terminal of the oscillator
17
e
and a connection node N
2
of the NMOS transistors
17
c
and
17
d.
In the above circuit arrangement, the oscillator
17
e
starts to oscillate when the level of a signal PMP supplied to one end of the NAND circuit of the oscillator
17
e
becomes high. The output signal of the oscillator
17
e
is supplied to both the connection node N
1
through a series circuit of the inverter circuits
17
f
and capacitor
17
g
and the connection node N
2
through a series circuit of the inverter circuits
17
h
and
17
i
and capacitor
17
j
. Thus, the connection nodes N
1
and N
2
sequentially increase in voltage and so does the output node OUT. As shown in
FIG. 23
, the output voltage becomes constant at voltage Vpp which strikes a balance between a current output from the booster circuit and a current consumed by a circuit (not shown) to which the output voltage is applied. To improve a voltage gain of the booster circuit, the threshold voltages of the NMOS transistors
17
b
,
17
c
and
17
d
are set low. Even though the threshold voltages become negative, the voltage gain can be improved if the period of a clock is sufficiently short. The NMOS transistors are therefore set at a threshold voltage of almost 0V.
The foregoing booster circuit temporarily stops operating when the signal PMP is at a low level. The potentials of the connection nodes N
1
and N
2
are then raised up to Vpp by a backflow of current from the output node OUT. If, then, the level of the signal PMP becomes high again to activate the booster circuit, the booster circuit operates out of a steady state for a while. The efficiency of the booster circuit or the ratio of output current to input current is considerably lowered, with the result that the booster circuit will be decreased in its operating stability. This problem depends upon the voltage amplitude of the capacitors and becomes more serious as the power supply voltage Vcc lowers. The prior art booster circuit is thus difficult to operate at a low voltage.
FIG. 24
illustrates another prior art booster circuit disclosed in J. C. Chen et al. 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 172-3, Jun. 1996. The booster circuit comprises a P-channel MOS transistor (referred to as a PMOS transistor)
19
b
connected between a power supply terminal
19
a
to which a power supply voltage Vcc is applied and an output node OUT, a capacitor
19
c
one end of which is connected to the output node OUT, series-connected inverter circuits
19
d
and
19
e
for supplying a capacitor driving signal PMP to the other end of the capacitor
19
c
, and NMOS transistors
19
f
and
19
g
, PMOS transistors
19
h
and
19
i
and an inverter circuit
19
j
for controlling the PMOS transistor
19
b
in response to a signal ACT. The sources of the NMOS transistors
19
f
and
19
g
are grounded. The capacitor driving signal PMP is generated in response to the signal ACT.
FIG. 25
shows an operation of the booster circuit illustrated in FIG.
24
. When the signal ACT is at a low level, the booster circuit is in a nonoperating state and the power supply voltage Vcc is output from the output node OUT via the PMOS transistor. If the signal ACT is set at a high level when the booster circuit starts to operate, the signal PMP at the power supply voltage Vcc is set at a high level in response to the signal ACT. Since the PMOS transistor
19
b
is then turned off, the output voltage is raised up to a voltage Vpp which depends upon a ratio of the capacity of a load (not shown) connected to the output node OUT and that of the capacitor
19
c.
In the booster circuit for boosting an output voltage in the ratio of the capacity of the load to that of the capacitor, the output voltage depends upon the power supply voltage Vcc and the charging voltage of the capacitor
19
c
. For this reason, when the power supply voltage Vcc decreases, the output node OUT is difficult to increase up to the voltage Vpp only by the single capacitor
19
c.
As described above, in the prior art booster circuit of
FIG. 22
which is repeatedly activated and inactivated, the potentials of connection nodes N
1
and N
2
are increased by a backflow of current from the output terminal in the transition from the inactive state to the active state. For this reason, the prior art booster circuit has a problem of decreasing in efficiency especially when a power supply voltage is low.
In the booster circuit of
FIG. 24
for boosting an output voltage in the ratio of the capacity of the load to that of the capacitor, a necessary booster voltage cannot be generated when a power supply voltage is low.
The same problems as above are true of a prior art negative voltage generating circuit.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in order to resolve the foregoing problems and its object is to provide a semiconductor device having a pump circuit capable of generating a given output voltage even when a power supply voltage is decreased.
To attain the above object, a pump circuit according to a first aspect of the present invention comprises: a plurality of switching elements connected in series between a first node to which a first voltage is applied and an output node from which a second voltage other than the first voltage is output; at least one capacitor having a first terminal and a second terminal, the first terminal of the capacitor being connected to at least one connection node of the plurality of switching elements; a signal generator connected to the second terminal of the capacitor, for generating a driving signal when a control signal is first logic and stopping generation of the driving signal when the control signal is second logic; and a reset circuit connected to the connection node, for resetting a voltage of the connection node to a third voltage other than the second voltage when the control signal changes from the second logic to the first logic.
According to a second aspect of the present invention, there is provided a pump circuit comprising: a first capacitor having a first terminal and a second terminal, the first terminal being connected to an output node; a second capacitor having a third terminal and a fourth terminal, the third terminal being supplied with a first signal in an active mode; a first reset circuit connected to the second terminal of the first capacitor, for resetting the second termin
Atsumi Shigeru
Tanzawa Toru
Banner & Witcoff , Ltd.
Callahan Timothy P.
Englund Terry L.
Kabushiki Kaisha Toshiba
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