Clock-independent latch setup-and-hold time in a combined D-type

Clocked flip flop circuit with built-in clock controller and fre

Clocked register

Clocked state devices including master-slave terminal...

Clocked-scan flip-flop for multi-threshold voltage CMOS circuit

CMOS comparator with hysteresis

CMOS latch having a selectable feedback path

CMOS level detection circuit with hysteresis having disable/enab

CMOS low-voltage dynamic back-gate forward bias prescaler

CMOS master/slave flip-flop with integrated multiplexor

CMOS strobed comparator with programmable hysteresis

CMOS switching circuitry

CMOS toggle flip-flop using adiabatic switching

Coherent multiplexer controller

Comparator and AD conversion circuit having hysteresis circuit

Comparator circuit with built-in hysteresis offset

Comparator circuit with hysteresis

Comparator circuit with Schmitt trigger hysteresis character

Comparator with hysteresis

Comparator with hysteresis and method of comparing using the...