CMOS comparator with hysteresis

Details CMOS comparator with hysteresis CMOS comparator with hysteresis

1999-06-01

2001-04-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S063000, C327S067000, C327S068000, C327S074000, C327S080000, C327S205000, C327S206000, C327S538000

Reexamination Certificate

active

06211712

ABSTRACT:

BACKGROUND
1. Technical Field
The present invention relates generally to a comparator and, more particularly, to a CMOS comparator with hysteresis.
2. Description of Related Art
In general, a comparator is a device which compares an input voltage with a reference voltage, amplifies the voltage differential between the input voltage and the reference voltage, and outputs a voltage signal of a high or low level based on the voltage differential. A comparator is typically employed in an analog-digital converter (such as a flash A/D converter), wherein an analog input signal is converted to a digital output signal by comparing the analog input signal with a plurality of reference voltages by using a complimentary metal-oxide semiconductor (CMOS) flash analog-digital converter.
Because of their high speed, flash analog-digital converters are widely employed in video devices, radar devices, laboratory instruments, and other devices which are used in high-speed applications. Other advantages associated with CMOS flash analog-digital converters are their compact size and low power dissipation, which enables them to be fabricated as monolithic integrated circuits.
For the comparator output voltage to be maintained at a high level state at a zero point, hysteresis is used to prevent the output voltage from changing as the input voltage is reduced. When the input voltage drops to a lower reference voltage (a negative trip point), the output voltage changes from the high level state to a low level state. The comparator output voltage will remain in the low level state as the input voltage increases. When the input voltage reaches an upper reference voltage (a positive trip point), the output voltage will change from the low level state to the high level state. The difference in voltage between the upper reference voltage and the lower reference voltage is known as the amount of the hysteresis. It is to be understood that the terms “high level state” (or “high”) and “low level state” (or “low”) used herein in connection with signals and logic levels are equivalent to logic levels “1” and “0”, respectively.
Referring to
FIG. 1
, a circuit diagram illustrates a conventional comparator with hysteresis. Although there are many techniques known by those skilled in the art for providing hysteresis in a comparator, all of the conventional techniques employ some form of positive feedback. Consider the differential input stage as shown in FIG.
1
. In this circuit, there are two feedback paths. The first feedback path is a current-series feedback through the common-source node of transistors M
1
and M
2
, which is a negative feedback path. The second feedback path is the voltage-shunt feedback through the gate-drain connections of transistors M
10
and M
11
, which is a positive feedback path. It is understood by those skilled in the art that if the positive feedback factor is less than the negative feedback factor, the overall feedback will be negative, thus resulting in no hysteresis. On the other hand, If the positive feedback factor is greater than the negative feedback factor, the overall feedback will be positive, which results in hysteresis (such as illustrated by the voltage transfer curve of FIG.
5
).
A comparator is typically employed in a noisy environment, thereby requiring hysteresis to ensure a noise margin. With the conventional comparator shown in
FIG. 1
, the desired amount of hysteresis can be determined in accordance with the ratio of size of MOS transistors. Unfortunately, in order to control the trip voltages (and, therefore, the amount of the hysteresis), the comparator must be entirely reconstructed or an additional process is required for changing the ratio of size of transistors. As a result, it difficult to control the amount of the hysteresis. Another problem is that the conventional comparator also includes bias circuitry, which adds to the difficulty in controlling the amount of hysteresis.
SUMMARY OF THE INVENTION
The present invention is directed to a comparator with hysteresis having a simplified architecture such that the amount of hysteresis can be readily adjusted.
In one aspect of the present invention, a comparator with hysteresis comprises:
a first switch for coupling an analog input voltage to a signal node in response to a first clock signal;
an inverter having an input port and an output port;
a capacitor operatively coupled between the signal node and the input port of the inverter;
a second switch operatively connected between the input port and the output port of the inverter, the second switch being responsive to the first clock signal;
a latch having a clock port, an output signal port, an inverse output signal port, and an input data port, the input data port being coupled to the output port of the inverter; and
a reference voltage control circuit for selectively outputting a first internal reference voltage and a second internal reference voltage to the signal node in response to the output signal and inverse output signal, respectively, received from the latch.
In another aspect of the present invention, the reference voltage control circuit has a logic circuit for outputting control signals responsive to a second clock signal and the output signals of the latch. A reference voltage generating circuit outputs selectively a first internal reference voltage and a second internal reference voltage among a plurality of the internal reference voltages based on a first and second external reference voltages to the signal node. Second analog switches outputs selectively one of the first and the second internal reference voltages to the signal node.
In yet another aspect of the present invention, the reference voltage control circuit of the comparator comprises:
a logic circuit for outputting one of a first and second control signal in response to a second clock signal and the output signal and inverse output signal of the latch;
a reference voltage generating circuit for outputting the first internal reference voltage and the second internal reference voltage to the signal node, the first internal reference voltage and the second internal reference voltage being selected from a plurality of available reference voltages generated by dividing a first and a second external reference voltage; and
a third and fourth switch for selectively outputting the first and second internal reference voltages, respectively, to the signal node, in response to the first and second control signals, respectively.
In another aspect of the present invention, a comparator having a controllable amount of hysteresis, comprises:
means for comparing an input voltage with one of an upper threshold voltage and a lower threshold voltage depending on an output state of the comparator, wherein the difference between the upper and lower threshold voltages is the amount of hysteresis; and
means for adjusting the amount of hysteresis by selecting a first one of a plurality of reference voltages as the upper threshold voltage and for selecting a second one of the plurality of reference voltages as the lower threshold voltage.
These and other aspects, features and advantages of the present invention will be described and become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 4433256 (1984-02-01), Dolikian
patent: 4992675 (1991-02-01), Conner, Jr. et al.
patent: 5047663 (1991-09-01), Lee et al.
patent: 5467009 (1995-11-01), McGlinchey
patent: 5990707 (1999-11-01), Goldenberg et al.

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